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1

Disaster response and river infrastructure management during the 2015 Myanmar floods: A case in the Bago River Basin

Kawasaki, Akiyuki, Ichihara, Nobuyuki, Ochii, Yasuhiro, Acierto, Ralph Allen, Kodaka, Akira, Zin, Win Win

Journal:

International Journal of Disaster Risk Reduction

Year:

2017

Language:

english

File:

PDF, 1.20 MB

english, 2017

2

Design of low-delay perfect-reconstruction filter banks using linear programming

Morihiko Ota, Yoshito Higa, Hiroshi Ochii

Journal:

Electronics and Communications in Japan (Part II: Electronics))

Year:

2001

Language:

english

File:

PDF, 301 KB

english, 2001

3

Three-layered microcapsules as a long-term sustained release injection preparation

Yukako Ito, Yuya Ochii, Keizo Fukushima, Nobuyuki Sugioka, Kanji Takada

Journal:

International Journal of Pharmaceutics

Year:

2010

Language:

english

File:

PDF, 565 KB

english, 2010

4

Consideration of poly-Si loaded cell capacity limits for low-power and high-speed SRAMs

Kato, H., Sato, K., Matsui, M., Shibata, H., Hashimoto, K., Ootani, T., Ochii, K.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1992

Language:

english

File:

PDF, 311 KB

english, 1992

5

SRAM cell stability under the influence of parasitic resistances and data holding voltage as a stability prober

Kato, H., Matsui, M., Sato, K., Shibata, H., Hashimoto, K., Ootani, T., Ochii, K.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1997

Language:

english

File:

PDF, 155 KB

english, 1997

6

A 4-Mb CMOS SRAM with a PMOS thin-film-transistor load cell

Ootani, T., Hayakawa, S., Kakumu, M., Aona, A., Kinugawa, M., Takeuchi, H., Noguchi, K., Yabe, T., Sato, K., Maeguchi, K., Ochii, K.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1990

Language:

english

File:

PDF, 942 KB

english, 1990

7

An ultralow power 8Kx8-bit full CMOS RAM with a six-transistor cell

Ochii, K., Hashimoto, K., Yasuda, H., Masuda, M., Kondo, T., Nozawa, H., Kohyama, S.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1982

Language:

english

File:

PDF, 1.08 MB

english, 1982

8

An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters

Matsui, M., Momose, H., Urakawa, Y., Maeda, T., Suzuki, A., Urakawa, N., Sato, K., Matsunaga, J., Ochii, K.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1989

Language:

english

File:

PDF, 1004 KB

english, 1989

9

[IEEE 1991 Symposium on VLSI Circuits - Oiso, Japan (May 30-June 1, 1991)] 1991 Symposium on VLSI Circuits - Data-line wiring delay reduction techniques for high-speed BiCMOS SRAM's

Urakawa, Y., Matsui, M., Suzuki, A., Kato, H., Hamano, T., Sato, K., Ohtani, T., Ochii, K.

Year:

1991

File:

PDF, 163 KB

1991

10

[IEEE 1977 IEEE International Solid-State Circuits Conference - Philadelphia, PA, USA (1977.02.16-1977.02.18)] 1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - C2MOS 4K static RAM

Ochii, K., Suzuki, Y., Ueno, M., Sato, K., Asahi, K.

Year:

1977

Language:

english

File:

PDF, 723 KB

english, 1977

11

[IEEE Digest of Technical Papers.1990 Symposium on VLSI Technology - Honolulu, Hawaii, USA (1990.06.4-1990.06.7)] Digest of Technical Papers.1990 Symposium on VLSI Technology - TFT (thin film transistor) cell technology for 4 Mbit and more high density SRAMs

Kinugawa, M., Kakumu, M., Yoshida, T., Nakayama, T., Morita, S., Kubota, K., Matsuoka, F., Oyamatsu, H., Ochii, K., Maeguchi, K.

Year:

1990

Language:

english

File:

PDF, 220 KB

english, 1990

12

[Institute of Electrical and Electronics Engineers 1985 IEEE International Solid-State Circuits Conference - New York, NY, USA (February 1985)] 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - A 17ns 64K CMOS RAM with a schmitt trigger sense amplifier

Ochii, K., Yasuda, H., Kobayashi, K., Kondoh, T., Masuoka, F.

Year:

1985

Language:

english

File:

PDF, 525 KB

english, 1985

13

[IEEE IEEE International Solid-State Circuits Conference - New York, NY, USA (15-17 Feb. 1989)] IEEE International Solid-State Circuits Conference - An 8 ns 1 Mb ECL BiCMOS SRAM

Matsui, M., Momose, H., Urakawa, Y., Maeda, T., Suzuki, A., Urakawa, N., Sato, K., Makita, K., Matsunaga, J., Ochii, K.

Year:

1989

Language:

english

File:

PDF, 349 KB

english, 1989

14

[IEEE 1992 Bipolar/BiCMOS Circuits and Technology Meeting - Minneapolis, MN, USA (7-8 Oct. 1992)] Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting - 3.3 volt sense-amplifier schemes suitable for 4 Mb BiCMOS SRAMs

Suzuki, A., Kato, H., Kobayashi, T., Hamano, T., Sato, K., Matsui, M., Urakawa, Y., Ochii, K.

Year:

1992

Language:

english

File:

PDF, 320 KB

english, 1992

15

[IEEE 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers - San Francisco, CA, USA (19-21 Feb. 1992)] 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers - A 9 ns 4 Mb BiCMOS SRAM with 3.3 V operation

Kato, H., Suzuki, A., Hamano, T., Kobayashi, T., Sato, K., Nakayama, T., Gojohbori, H., Maeda, T., Ochii, K.

Year:

1992

File:

PDF, 198 KB

1992

16

[Institute of Electrical and Electronics Engineers 1986 IEEE International Solid-State Circuits Conference - Anaheim, CA, USA (February 1986)] 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - A 18ns 8KW × 9b NMOS RAM

Segawa, M., Ariizumi, S., Suzuki, Y., Kondo, T., Ando, T., Ochii, K., Masuoka, F.

Year:

1986

Language:

english

File:

PDF, 541 KB

english, 1986

17

[IEEE 1993 Symposium on VLSI Circuits - Kyoto, Japan (1997.06.14-1997.06.14)] Symposium on VLSI Circuits - High-speed and low-standby-power circuit design of 1 to 5 V operating 1 Mb full CMOS SRAM

Yabe,, Matsuoka,, Sato,, Hayakawa,, Sato,, Matsui,, Aono,, Yoshimura,, Ishimaru,, Gojohbori,, Morita,, Unno,, Kakumu,, Ochii,

Year:

1993

Language:

english

File:

PDF, 198 KB

english, 1993

18

[IRE 1985 International Electron Devices Meeting - ()] 1985 International Electron Devices Meeting - A new high density full CMOS SRAM cell using polysilicon interconnection structure

Masuoka, F., Ochii, K., Masuda, M., Kobayashi, K., Kondo, T.

Year:

1985

Language:

english

File:

PDF, 222 KB

english, 1985

19

[IEEE 37th IEEE International Conference on Solid-State Circuits - San Francisco, CA, USA (14-16 Feb. 1990)] 37th IEEE International Conference on Solid-State Circuits - A 1 mu A retention 4 Mb SRAM with a thin-film-transistor load cell

Hayakawa, S., Kakumu, M., Takeuchi, H., Sato, K., Ohtani, T., Yoshida, T., Nakayama, T., Morita, S., Kinugawa, M., Maeguchi, K., Ochii, K., Matsunaga, J., Aono, A., Noguchi, K., Asami, T.

Year:

1990

Language:

english

File:

PDF, 1.76 MB

english, 1990

20

[IEEE 1980 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA (1980.02.13-1980.02.15)] 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - Fully static 16Kb bulk CMOS RAM

Iizuka, T., Ochii, K., Ohtani, T., Kondo, T., Koyhama, S.

Year:

1980

Language:

english

File:

PDF, 511 KB

english, 1980

21

[IEEE 1991 Symposium on VLSI Circuits - Oiso, Japan (May 30-June 1, 1991)] 1991 Symposium on VLSI Circuits - Consideration Of Poly-SI Loaded Cell Capacity Limits For Each Of Low-power And High-speed SRAM's

Kato, H., Sato, K., Matsui, M., Shibata, H., Hashimoto, K., Ohtani, T., Ochii, K.

Year:

1991

File:

PDF, 144 KB

1991

22

[IEEE 1982 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA (1982.02.10-1982.02.12)] 1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - A 15nW standby power 64Kb CMOS RAM

Ochii, K., Hashimoto, K., Yasuda, H., Masuda, M., Nozawa, H., Kohyama, S.

Year:

1982

Language:

english

File:

PDF, 513 KB

english, 1982

23

Isolation of Persicarin from Oenanthe Stolonifera DC.

Tatsuta, Haruo, Ochii, Yasuko

Journal:

Nippon kagaku zassi

Year:

1954

File:

PDF, 325 KB

1954

24

Decarbonylation of Aromatic Aldehydes.

Tatsuta, Haruo, Ochii, Yasuko

Journal:

Nippon kagaku zassi

Year:

1954

File:

PDF, 164 KB

1954